Download e-book for iPad: Analog Circuit Design: High-speed Clock and Data Recovery, by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

ISBN-10: 1402089430

ISBN-13: 9781402089435

Analog Circuit layout includes the contribution of 18 tutorials of the seventeenth workshop on Advances in Analog Circuit layout. each one half discusses a particular to-date subject on new and precious layout rules within the region of analog circuit layout. each one half is gifted through six specialists in that box and state-of-the-art details is shared and overviewed. This ebook is quantity 17 during this profitable sequence of Analog Circuit layout.

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Extra info for Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management

Example text

Fractional-N Synthesis: Non-Linear Analysis The linear analysis suggested that applying control to the prescaler would not cause any problems whatsoever. Practice however proves this inaccurate. Therefore, an analysis method is developed that provides a fast, interactive means of examining the influence of non-linearities and mismatch in different PLL building blocks by performing a transient simulation of the fractional-N synthesizer. The strong point of the analysis method is its capability to sweep simulations sufficiently fast over different degrees of non-linearities and operating points, while performing sufficiently long transient simulations to get accurate fast-Fourier transforms (FFT) of the phase variable.

5. Impact of Open Loop Parameter Variations In a practical PLL implementation, the value of the open loop gain and loop filter pole and zero locations will vary from chip to chip and across temperature. Classical PLL design methodologies address this issue by examining the phase margin of the open loop transfer function across all such variations to infer whether the system remains stable. The problem with this approach is that it provides little information on other important issues such as the change in settling time or closed loop transfer function that will occur due to such changes.

92. 08 MHz offset from an integer multiple of In Fig. 8 (c) and (d), the time-domain phase error is plotted for both modulators.

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Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier


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