60-GHz CMOS Phase-Locked Loops - download pdf or read online

By Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund

ISBN-10: 904819279X

ISBN-13: 9789048192793

The promising excessive facts fee instant purposes at millimeter wave frequencies mostly and 60 GHz specifically have won a lot realization lately. although, demanding situations on the topic of circuit, format and measurements in the course of mm-wave CMOS IC layout must be conquer earlier than they could turn into achievable for mass market.

60-GHz CMOS Phase-Locked Loops concentrating on phase-locked loops for 60 GHz instant transceivers elaborates those demanding situations and proposes suggestions for them. The process point layout to circuit point implementation of the whole PLL, in addition to separate implementations of person parts comparable to voltage managed oscillators, injection locked frequency dividers and their combos, are incorporated. in addition, to fulfill a couple of transceiver topologies concurrently, flexibility is brought within the PLL structure through the use of new dual-mode ILFDs and switchable VCOs, whereas reusing the low frequency parts on the comparable time.

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Extra resources for 60-GHz CMOS Phase-Locked Loops

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M. V. 2010 35 36 3 Layout and Measurements at mm-Wave Frequencies different device orientation also become visible. Owing to low-resistivity, CMOS substrates incur losses for passive structures such as inductors, transformers and transmission lines, degrading their high frequency performance. Furthermore, cross-talk between RF interconnects in close proximity deteriorates the spectral purity of signals and requires isolation and shielding from each other. Variation in ground potential in different parts of the integrated circuit generates erroneous voltage levels and innovative grounding techniques are required to achieve a common reference voltage all over the chip.

To estimate the settling time, the division ratio is first changed to 131 and then incremented to 136. This corresponds to a 500 MHz and 2 GHz frequency jump at 60 GHz, respectively. The settling time obtained is about 1 ms as shown in Fig. 13. The ideal output of a frequency synthesizer is a pure sinusoidal waveform. However, just like any other integrated electronic system, non-idealities such as noise degrade the spectrum purity of the output signal. This can potentially result (among other negative impacts) in lower sensitivity, poor blocking performance on the receiver side, and increased spectral emissions on the transmitter side.

The small dimensions contribute to signal loss which typically rises with frequency. In case of coaxial cables, impedance and insertion loss varies with different cable routing. Furthermore, bending and stretching cables changes their dimensions, and thus affects signal propagation. This is particularly critical when measuring phase sensitive circuits (I-Q VCOs, phase shifters etc) where matching is of utmost importance. To address the above mentioned source of inaccuracies, semi-rigid cables and solid waveguides are employed in this work to minimize connection variations during measurements and enable accurate measurements.

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60-GHz CMOS Phase-Locked Loops by Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund

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